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Macros</h2></td></tr>
<tr class="memitem:ga88e5d3fa1470e0fef0ae45c4956f1fa3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga88e5d3fa1470e0fef0ae45c4956f1fa3">XSrio_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="separator:ga88e5d3fa1470e0fef0ae45c4956f1fa3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f54b6fbef6410f2c375bde9e7bf09bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga7f54b6fbef6410f2c375bde9e7bf09bd">XSrio_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="separator:ga7f54b6fbef6410f2c375bde9e7bf09bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr class="memitem:gabab5f1195566978a3b8d7547b6c4e0a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gabab5f1195566978a3b8d7547b6c4e0a3">XSRIO_DEV_ID_CAR_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
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<tr class="memitem:ga2b32c0953d0a478feea6138775413b63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2b32c0953d0a478feea6138775413b63">XSRIO_PELL_CTRL_CSR_OFFSET</a>&#160;&#160;&#160;0x4c</td></tr>
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<tr class="memitem:ga2e147a812705dfde71c8b3b5ea85b7e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2e147a812705dfde71c8b3b5ea85b7e0">XSRIO_EFB_HEADER_OFFSET</a>&#160;&#160;&#160;0x100</td></tr>
<tr class="separator:ga2e147a812705dfde71c8b3b5ea85b7e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed9939e0409d3c884a5d6040818f30f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaed9939e0409d3c884a5d6040818f30f5">XSRIO_IMP_WCSR_OFFSET</a>&#160;&#160;&#160;0x10000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Device Identity CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_DEV_ID_CAR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Device Information CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_DEV_INFO_CAR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Assembly Identity CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_ASM_ID_CAR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Assembly Device Information CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_ASM_INFO_CAR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Processing Element Features CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PEF_CAR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Source Operations CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_SRC_OPS_CAR_OFFSET register and XSRIO_DST_OPS_CAR register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">PE Logical layer Control CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PELL_CTRL_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Local Configuration Space Base Address 1 CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_LCS1_BASEADDR_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Base Device ID CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_BASE_DID_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Host Base Device ID CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_HOST_DID_LOCK_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">LP - Serial Register Block header bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_EFB_HEADER_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Port Link timeout value CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_LINK_TOUT_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Port response timeout value CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_RESP_TOUT_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Port General Control CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_GEN_CTL_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n maintenance request CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_MNT_REQ_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n maintenance response CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_MNT_RES_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n local ack ID CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_ACKID_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n Error and Status CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_ERR_STS_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n Control CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_CTL_CSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">LP -Serial Lane Register Block Header bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_SL_HEADER_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">LP -Seral Lane n Status 0 CSRS bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_SLS0_CSR(x) register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">LP -Seral Lane n Status 1 CSRS bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_SLS1_CSR(x) register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Water Mark CSRS bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_IMP_WCSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Buffer Control CSRS bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_IMP_BCSR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Maintenance Request Information Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_IMP_MRIR_OFFSET register. </p>
</div></td></tr>
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